News

Design And Reuse17m
The RISC-V World Sees Changes, Milestones, and Innovations
In fifteen years, RISC-V has gone from an academic project at UC Berkeley to one of the major technological trends in compute. The ISA has since flourished in an era that appreciates its royalty-free, ...
Design And Reuse1h
SiFive Collaborates with Red Hat to Support Red Hat Enterprise Linux for RISC-V
"Native Red Hat Enterprise Linux support on SiFive’s HiFive Premier P550 board offers developers a substantial enterprise-grade toolchain for RISC-V. This is a pivotal step forward in enabling a ...
Design And Reuse1h
EnSilica expands satcoms user terminal portfolio with dual-beam, dual-polarization Ku-band analogue beamformer chipset
The ENS92051 is the dual-beam Ku-band receiver (Rx) supporting eight channels with separate amplitude and phase control. The Rx carrier frequency range is 10.7 to 12.75 GHz with an instantaneous ...
Design And Reuse1h
GlobalFoundries partners with A*STAR to accelerate advanced packaging innovation
SINGAPORE -- May, 20 2025 – GlobalFoundries (Nasdaq: GFS) (GF) today announced plans to expand its capabilities in advanced packaging through a new Memorandum of Understanding (MOU) signed with the ...
Design And Reuse18h
Creonic Adds oFEC Codec IP Core to Portfolio, Expanding High-Speed Networking Solutions for ASIC and FPGA
Creonic GmbH, a leading provider of ready-to-use IP cores for ASIC and FPGA applications, announces the release of its new oFEC (Open Forward Error Correction) codec IP core. The solution supports ...
Design-Reuse19h
Vivante GC7000 GPUs Deliver Desktop-Class Graphics to Mobile Devices
Sunnyvale, CA – April 3 rd, 2014 – Vivante Corporation today announced multiple silicon partner integrations of its GC7000 Series GPU IP into SoCs targeting wearables, mobile, automotive, and 4K TV ...
Design And Reuse1d
Expedera s Origin Evolution NPU IP Brings Generative AI to Edge Devices
Expedera launches its Origin Evolution NPU IP, bringing hardware acceleration to meet the computational demands of running ...
Design And Reuse1d
PolarFire Core devices streamline costs while retaining the market-leading power efficiency, security and reliability of classic PolarFire families
PolarFire Core devices are supported by Microchip’s Libero® SoC Design Suite, SmartHLS™ compiler, VectorBlox™ Accelerator SDK and Microchip’s Mi-V ecosystem of partner platforms for rapid RISC-V ...
Design And Reuse1d
Boosting RISC-V SoC performance for AI and ML applications
At around the same time, the open and configurable RISC-V instruction set architecture (ISA) is experiencing rapid adoption across diverse markets. This growth aligns with rising SoC complexity and ...
Design And Reuse1d
BrainChip CTO to Present on Architectural Innovation for Low-Power AI at the Embedded Vision Summit
Attendees of the Summit can visit BrainChip at booth #716 to see live demonstrations of the company’s latest advancements in Edge AI technology, including innovations in on-chip language processing, ...
Design-Reuse1d
System Verilog + OVM: Mitigating Verification Challenges & Maximizing Reusability
Verification – has been becoming a nightmare for engineers with the increasing requirements and complexity of the design. Mitigating the complexity of a verification environment with the increasing ...
Design-Reuse1d
Lattice Propel Design Environment Supports New RISC-V Processor and IP Cores
HILLSBORO, OR – May 19, 2021 – Lattice Semiconductor (NASDAQ: LSCC), the low power programmable leader, today announced a new version of Lattice Propel™, a design environment for accelerating embedded ...